A Fault Tolerant and Power Efficient Network-on-Chip Architecture using Quad-Function Channel (QFC) Buffers

Case ID:
UA14-104
Invention:

QORE is a fault tolerant Different Network on Chip (NoCs) that seeks to reduce power consumption and improve performance of NoCs while mitigating errors caused by faults. Through a new type of data buffer and connecting multiple processing cores QORE has the ability to reduce power and avoid faults.


Background:

With electrical components shrinking in size, there has been remarkable growth in the number of cores that can be integrated within a single chip multiprocessor. As the number of cores continue to scale and conventional on-chip communications approach their limits, architects are urged to consider other scalable communication strategies. Different Network on Chips (NoCs) configurations have been a viable tool in order to overcome these limits but has come at great costs, including a power and area expense which has adversely affected NoC performance.
 

Applications:

  • For network-on chips connecting multiple processing cores
  • General purpose computing on graphics processing units
  • Mobile industries
  • Workstations
  • Servers
  • Consumer electronics


Advantages:

  • Ability to reduce power and avoid faults
  • Scale future multi-core chips and SoCs to a much higher core numbers and much higher performance levels

 

Status: issued patent #10,148,593

Patent Information:
Contact For More Information:
Tariq Ahmed
Sr Licensing Manager, College of Engineering
The University of Arizona
tariqa@tla.arizona.edu
Lead Inventor(s):
Avinash Kodi
Dominic Ditomaso
Ahmed Louri
Keywords: