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Fault- and Variation-Tolerant Energy- and Area-Efficient Links for Network-on-Chips (NoCs)
Researchers in the University of Arizona's Department of Electrical and Computer Engineering developed an enhancement to the Inter-Router Dual-Function Energy and Area Efficient Links (iDEAL) design for Network-on-Chips (NoC). This development adds dynamic error correction and fault-tolerance capability to the iDEAL design scheme and overcomes many...
Published: 4/3/2023
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Inventor(s): Ahmed Louri, Janet Roveda, Avinash Kodi, Ashwini Sarathy
Keywords(s):
Category(s): Technology Classifications > Engineering & Physical Sciences, Technology Classifications > Engineering & Physical Sciences > Electronics, Technology Classifications > Engineering & Physical Sciences > Electronics > Digital Circuits, Technology Classifications > Engineering & Physical Sciences > Communications & Networking, Technology Classifications > Engineering & Physical Sciences > Communications & Networking > Networking
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