Invention:
This technology provides a computational approach that effectuates fully automated Network-on-Chip (NOC) design and optimization that is also applicable to processor design. The approach explores the network configuration space to determine, e.g., optimal network latencies, power consumption, and the underlying link/interconnect allocations for any given number of routers, i.e., the ab initio network-on-chip design.
Background:
Multi-core processors have enabled ongoing computer performance improvement (i.e., trying to keep Moore’s law alive) but at the cost of increasing complexity of network design. Most network design is optimized for bandwidth but, for any given bandwidth design, there is a need to address tradeoffs between parameters, such as, but not limited to, latency and power, the latter also being responsible for heat generation. Using a Pareto-optimal design framework, this technology automatically generates ab initio network designs that optimize those tradeoffs according to user specifications or requirements. As such, it is a critical capability that directly supports the bipartisan CHIPS and Science Act of 2022.
Applications:
- Integration with Network-on-Chip electronic design automation tools
- Processor design
Advantages:
- Effectively determines the layout of NOC topologies, i.e. the ab initio NOC design
- Optimizes Network-on-Chip interconnect layout
- Allows for tradeoff studies (e.g. network latency vs. power)
Status: issued U.S. patents #11,544,441 and #11,960,815
