Invention:
This technology provides a computationally efficient method for designing Network-on-Chips (NOCs) interconnects for System-on-Chips (SOCs). The approach optimizes power and latency in O(n^4) versus alternative methods that are O(2^n).
Background:
Multi-core processors have enabled ongoing computer performance improvement but at the cost of increasing complexity of network design. Most network design is optimized for bandwidth but, for any given bandwidth design, there is a need to address tradeoffs between latency and power. This technology provides a computationally efficient way to identify designs that optimize those tradeoffs.
Applications:
- Integration with Network-on-Chip electronic design automation tools
Advantages:
- Computationally efficient
- Optimizes Network-on-Chip interconnect design
Status: issued U.S. patents #11,544,441 and #11,960,815
